2d:null 2e:["$","title",null,{"children":"duh orconf2019 | Aliaksei Chapyzhenka | Observable"}] 33:Tad3,pitch = { // Current collection of transitions and classes, current slide var transition = "", extra="", curslide = -1, parent=undefined, timer=undefined, autonext=0, speak=''; // String template (or html element). Calls through to Markdown. var pitch = function(a,...r) { const div = Object.assign(html`

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\n\n# Reusing HW components with

flow\n\n

\n Aliaksei Chapyzhenka
@wavedrom\n

\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":21,"value":"pitch`\n\n

\n\n

SoC Integration

\n\n* HW componets (aka IP block)\n* instantiate, configure, generate\n* Interconnect\n* Clock, Reset, Power plumbing\n* DFx\n* Test\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":31,"value":"md`\n\nIntegration Takes Time = $$$\n\nComponents comes from different sources.\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":24,"value":"pitch`\n

\n\n

Component reuse

\n\n* Share development cost\n* Improve quality\n* Reduce risk\n* Accelerate development cycle\n* Close or Open source\n* Good documentation\n* Configurability\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":25,"value":"md`\nTypical “reusable” Soft / Hard core component comes with the intricate integration story hopefully described in some human readable User Guide document.\n\nConnecting all ports, parameters, registers, bus interfaces, clocks, resets, sideband signals, etc. becoming a very tedious, error prone process.\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":39,"value":"pitch`\n

\n\n## DUH = HW Manifesto\n\n* Metadata exchange JSON5 format\n* JSON Schema\n* Collection of tools\n* OpenSource Apache 2.0\n\nhttps://github.com/sifive/duh\n \n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":65,"value":"pitch`\n

\n\n## DUH document types\n\n* Component\n* Bus interface definitions\n* Design (composition)\n* Configuration\n\nhttps://github.com/sifive/duh-schema\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":77,"value":"pitch`\n

\n\n## DUH bus definitions\n\n* AMBA, Memory, Generic, ...\n* Master / Slave requirements, attributes,\n* Referenced in the components and designs\n* Can be used for validation, integration\n* Shared across multiple components\n\nhttps://github.com/sifive/duh-bus\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":70,"value":"pitch`\n

\n\n## DUH components\n\n* Parameter schema\n* Ports\n* Bus interface\n - port mappings\n - attributes, properties\n* Memory maps\n - Address blocks\n - Registers, Fields\n* ...\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":107,"value":"pitch`\n

\n\n## DUH tools\n\n* Creation / Authoring\n* Import\n - Verilog, SystemRDL, IP-XACT\n* Inference\n - Standard Bus Interface mappings\n* Validation\n* Configuration / Composition\n* Export\n - Verilog, IP-XACT, SystemC, Chisel/Diplomacy\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":119,"value":"pitch`\n

\n\n## Import\n\n### Parsers\n\n* Verilog 2017 https://github.com/tree-sitter/tree-sitter-verilog\n* SystemRDL 2.0 https://github.com/drom/tree-sitter-systemrdl\n* FIRRTL https://github.com/chipsalliance/tree-sitter-firrtl\n\nIP-XACT https://github.com/sifive/duh-ipxact\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":122,"value":"pitch`\n

\n\n## DUH inference\n\nPort ⇒ Bus interfaces\n\nhttps://github.com/sifive/duhportinf\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":125,"value":"md`\n\nInference tools helps to reason about structure of the ports, standard bus interfaces, clocks, resets.\n\nValidation tools helps document author to maintain complete and consistent DUH document describing specific hardware component.\nIntegration tools can read DUH documents to understand and satisfy an integration needs of these components.\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":129,"value":"pitch`\n

\n\n## DUH document validation\n\n* format\n* completeness\n* consistency\n\nhttps://github.com/sifive/duh\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":132,"value":"pitch`\n

\n\n## DUH export tools\n\n* Scala (Chisel) https://github.com/sifive/duh-scala\n* Documentation \n* SystemC\n* Verilog Black Box\n* IP-XACT\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":135,"value":"pitch`\n

\n\n## Enable tools for\n\n* Component configuration\n* System integration\n* Database Query / Search\n* Analysis\n* UI\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":138,"value":"pitch`\n

\n\n## Open HW Manifesto\n\nhttps://duh.run\n\n\\`\\`\\`\nnpm i duh\n\\`\\`\\`\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":143,"value":"pitch`\n

\n\n

\n\n`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":5,"value":"md`### Appendix`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":9,"value":"$33","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":12,"value":"md`Style ↴`","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"},{"id":15,"value":"$34","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","output":"$undefined","database":"$undefined"}],"files":"$W35","stdlib":"1","titling":"auto"}} 32:"$31:body"