2c:null 2d:["$","title",null,{"children":"SPI Timing Constraints | Neil Turley | Observable"}] 32:Tf88,viewof params = { const form = html`

Reference Clock:

Output Clock:

Port:

Falling Edge:

High Clocks:

Low Clocks:

Output Data:

Launch Offset:

Falling Edge:

Setup:

Hold:

Input Data:

Falling Edge:

Minimum Output Delay:

Maximum Output Delay:

Latch Offset:

`; form.oninput = () => form.value = { RefClk : form.RefClk.value, OutClk : form.OutClk.value, OutClkPort : form.OutClkPort.value, OutReg : form.OutReg.value, IsFallingEdge : form.IsFallingEdge.checked, HighClks : form.HighClks.valueAsNumber, LowClks : form.LowClks.valueAsNumber, OutData : form.OutData.value, LaunchOffset : form.LaunchOffset.valueAsNumber, LatchFallingEdge : form.LatchFallingEdge.checked, Setup : form.Setup.valueAsNumber, Hold : form.Hold.valueAsNumber, InData : form.InData.value, LaunchFallingEdge : form.LaunchFallingEdge.checked, MinClkToQ : form.MinClkToQ.valueAsNumber, MaxClkToQ : form.MaxClkToQ.valueAsNumber, LatchOffset : form.LatchOffset.valueAsNumber }; form.oninput(); return form; }33:T6fd,md` ## Introduction These constraints apply to an interface synchronous to some reference clock that generates a divided output clock, and drives and receives data synchronous to that same reference clock. Most SPI masters conform to this design pattern. ## Constraints ~~~~tcl create_generated_clock -name ${ params.OutClk } -edges ${ edges } -source [get_pins ${ params.OutReg }/C] [get_ports ${ params.OutClkPort }] set_output_delay -clock [get_clocks ${ params.OutClk }]${ params.IsFallingEdge?" -clock_fall":"" } -max ${ params.Setup } [get_ports ${ params.OutData }] set_output_delay -clock [get_clocks ${ params.OutClk }]${ params.IsFallingEdge?" -clock_fall":"" } -min -${ params.Hold } [get_ports ${ params.OutData }] set_multicycle_path -setup -start ${ Math.ceil(params.LaunchOffset) } -from [get_clocks ${ params.RefClk }] -through [get_ports ${ params.OutData }] -to [get_clocks ${ params.RefClk }] set_multicycle_path -hold -start ${ params.HighClks + params.LowClks + 1 } -from [get_clocks ${ params.RefClk }] -through [get_ports ${ params.OutData }] -to [get_clocks ${ params.RefClk }] set_input_delay -clock [get_clocks ${ params.OutClk }]${ params.IsFallingEdge?"-clock_fall ":"" } -max ${ params.MaxClkToQ } [get_ports ${ params.InData }] set_input_delay -clock [get_clocks ${ params.OutClk }]${ params.IsFallingEdge?"-clock_fall ":"" } -min ${ params.MinClkToQ } [get_ports ${ params.InData }] set_multicycle_path -setup -end ${ Math.ceil(params.LatchOffset) } -from [get_clocks ${ params.OutClk }] -through [get_ports ${ params.InData}] -to [get_clocks ${ params.RefClk }] set_multicycle_path -hold -end ${ params.HighClks + params.LowClks + 1 } -from [get_clocks ${ params.OutClk }] -through [get_ports ${ params.InData }] -to [get_clocks ${ params.RefClk }] ~~~ `34:T82b,md` ## Validation The following command should show a \`${ params.RefClk }\` edge as the launch clock the correct number of \`${ params.RefClk }\` cycles before the \`${ params.OutClk }\` edge as the latch clock. If \`${ params.OutData }\` refers to multiple ports, \`-max_paths\` can be used to capture the expected number of paths. ~~~~tcl report_timing -through [get_ports ${ params.OutData }] ${ params.LatchFallingEdge ? "-fall_to":"-rise_to"} [get_clocks ${ params.OutClk }] -delay_type max ~~~ The following command should show a \`${ params.RefClk }\` edge as the launch clock the correct number of \`${ params.RefClk }\` cycles after the \`${ params.OutClk }\` edge as the latch clock. ~~~~tcl report_timing -through [get_ports ${ params.OutData }] ${ params.LatchFallingEdge ? "-fall_to":"-rise_to"} [get_clocks ${ params.OutClk }] -delay_type min ~~~ The following command should not find any paths since it indicates the wrong latch edge for \`${ params.OutClk }\`. ~~~~tcl report_timing -through [get_ports ${ params.OutData }] ${ params.LatchFallingEdge ? "-rise_to":"-fall_to"} [get_clocks ${ params.OutClk }]\n\ ~~~ The following command should show a \`${ params.RefClk }\` edge as the latch clock the correct number of \`${ params.RefClk }\` cycles after the \`${ params.OutClk }\` edge as the launch edge. ~~~~tcl report_timing -through [get_ports ${ params.InData }] -fall_from [get_clocks ${ params.OutClk }] -delay_type max ~~~ The following command should show a \`${ params.RefClk }\` edge as the latch clock the correct number of \`${ params.RefClk }\` cycles before the \`${ params.OutClk }\` edge as the launch edge. ~~~~tcl report_timing -through [get_ports ${ params.InData }] ${ params.LatchFallingEdge? "-fall_to":"-rise_to"} [get_clocks ${ params.OutClk }] -delay_type min ~~~ The following command should not find any paths since it indicates the wrong launch edge for \`${ params.OutClk }\`. ~~~~tcl report_timing -through [get_ports ${ params.InData }] ${ params.LatchFallingEdge? "-rise_to":"-fall_to"} [get_clocks ${ params.OutClk }] ~~~ `35:T13ee,md` ## Detailed Explanation \`${ params.OutClk }\` is (assumed to be) the output of a flip-flop that is clocked by \`${ params.RefClk }\`, and has distinct high and low times as controlled by some state machine synchronous to \`${ params.RefClk }\`. In many cases \`${ params.OutClk }\` has a 50% duty cycle, but the parameters High Clocks and Low Clocks allow this to be specified explicitly. A generated clock is created with the -edges argument to indicate which edges of \`${ params.RefClk }\` create edges of \`${ params.OutClk }\`. Note that even if \`${ params.OutClk }\` is an even number of \`${ params.RefClk }\` cycles and has a 50% duty cycle, explicitly defining the relationship with -edges is preferred. Source clock edges are numbered from 1. The first two elements in the edges list are the edge numbers of \`${ params.RefClk }\` that cause the rising edge and the falling edge of \`${ params.OutClk }\`. The third element is the edge number of \`${ params.RefClk }\` at which point the \`${ params.OutClk }\` pattern should repeat. If \`${ params.OutClk }\` is generated from falling edges of \`${ params.RefClk }\`, even numbered edge indices must be specified. The generated clock is defined at the output port rather than at the Q pin of the flip-flop. So long as the generated clock is not used to clock any internal registers, this is generally preferable. If the generated clock is used as a clock inside the design, two generated clocks will likely be required: one at the Q pin of the flip-flop, and the second at the output port, with a -divide_by 1 relationship to the first generated clock. ${ params.OutData } is also driven from a flip-flop synchronous to \`${ params.RefClk }\`. The maximum output delay is specified as the datasheet setup requirement plus whatever worst case skew could exist between \`${ params.OutClk }\` and ${ params.OutData } arriving at the external slave. By default, the launch edge for setup analysis would be the \`${ params.RefClk }\` edge one cycle prior to the \`${ params.RefClk }\` edge that causes the latch edge of \`${ params.OutClk }\` (which is the latch edge because of the output delay constraint). The multicycle path for setup moves the launch (-start) edge back to the actual edge that launches the data. Note that if the Launch Offset is 1, the setup multicycle path can be omitted, but the hold MCP would still be required (as described below), and for the sake of more readable constraints, the setup MCP may be retained, even though it has no effect. The minimum output delay for ${ params.OutData } is the datasheet hold requirement plus whatever worst case skew could exist between \`${ params.OutClk }\` and ${ params.OutData } arriving at the external slave. Note that this is specified as a positive number indicating required stable time after the latch edge, but then the negative of this value is applied as the output delay constraint. The best way to think about this is that a negative output delay acts like a negative delay line outside the IC being constrained, so the internal FPGA logic will be required to provide at least that much delay. By default the launch edge for hold analysis is one launch clock edge after that used for setup analysis. With no multicycle paths applied, this would be the same \`${ params.RefClk }\` edge that causes the \`${ params.OutClk }\` latch edge. Once the setup multicycle path is applied, the hold launch edge also moves earlier by the same amount as setup. Since the hold check is verifying that the data does not change too early, we actually want to move the hold launch edge forward to the next time it can launch. Assuming ${ params.OutData } can only launch on one \`${ params.RefClk }\` edge out of the whole \`${ params.OutClk }\` cycle, then the hold multicycle path should move hold by the total number of \`${ params.RefClk }\` cycles in \`${ params.OutClk }\` minus one. \`${ params.InData }\` is driven by the external slave synchronous to the launch edge of \`${ params.OutClk }\` with some minimum and maximum delay. The state machine determines the \`${ params.RefClk }\` cycle on which \`${ params.InData }\` will be captured. The input delay constraints are the datasheet minimum and maximum clock to out, plus the propagation time for \`${ params.OutClk }\` to the slave and \`${ params.InData }\` back to the IC (using minimum or maximum as appropriate). Again by default, the setup analysis will select as the latch edge the next \`${ params.RefClk }\` rising edge after the \`${ params.OutClk }\` launch edge. The multicycle path moves the latch edge (-end) forward to the actual \`${ params.RefClk }\` edge that captures \`${ params.InData }\`. It is the designer’s responsibility to verify that the constraints match the implementation. As with \`${ params.OutData }\`, since there is a single \`${ params.RefClk }\` edge that latches \`${ params.InData }\` during the \`${ params.OutClk }\` cycle, the hold multicycle path moves the latch edge forward by a complete \`${ params.OutClk }\` cycle less one \`${ params.RefClk }\` cycle. `36:T460,timing = { // we are building this piece at a time, because they reference each other let t = {}; // Everything is in terms of edges, of which there are two per RefClk period t.outClkPeriod = 2 * (params.HighClks + params.LowClks); t.outClkInitRe = params.IsFallingEdge ? 2 : 1; t.outClkFe = t.outClkInitRe + 2 * params.HighClks; t.outClkRe = t.outClkFe + 2 * params.LowClks; t.outDataLatchSetup = params.LatchFallingEdge? t.outClkFe : t.outClkRe; t.outDataLaunch = t.outDataLatchSetup - 2 * params.LaunchOffset; t.outDataLatchHold = t.outDataLatchSetup - t.outClkPeriod; t.inDataLaunch = params.LatchFallingEdge? t.outClkFe : t.outClkInitRe; t.inDataLatchSetup = t.inDataLaunch + 2 * params.LatchOffset; t.inDataLatchHold = t.inDataLatchSetup - t.outClkPeriod; // Determine the full range to display t.startEdgeIdx = Math.min(1, t.outDataLatchHold, t.inDataLatchHold) - 1; if (t.startEdgeIdx % 2 == 1) { t.startEdgeIdx -= 1; } t.stopEdgeIdx = Math.max(t.outClkRe, t.outDataLatchSetup, t.inDataLatchSetup) + 2; t.totalTicks = t.stopEdgeIdx - t.startEdgeIdx + 1; return t; }37:Taee,wave = { let refClkWave = Array(timing.totalTicks).fill('').map((_, i) => i % 2? 'h':'l'); let refClkNode = Array(timing.totalTicks).fill('.'); refClkNode[indices.outDataLaunch] = 'X'; refClkWave[indices.outDataLaunch] = refClkWave[indices.outDataLaunch].toUpperCase(); refClkNode[indices.inDataLatchSetup] = 'Y'; refClkWave[indices.inDataLatchSetup] = refClkWave[indices.inDataLatchSetup].toUpperCase(); refClkNode[indices.inDataLatchHold] = 'Z'; refClkWave[indices.inDataLatchHold] = refClkWave[indices.inDataLatchHold].toUpperCase(); let outClkWave = Array(timing.totalTicks).fill('').map( (_,i) => { if (!((i - indices.outClkRe) % timing.outClkPeriod)) return '1'; if (!((i - indices.outClkFe) % timing.outClkPeriod)) return '0'; return '.'; }); outClkWave[0] = outClkWave.find( x => x != '.') == '1'?'0':'1'; let outClkNode = Array(timing.totalTicks).fill('.'); outClkNode[indices.outDataLatchHold] = 'P'; outClkNode[indices.outDataLatchSetup] = 'Q'; outClkNode[indices.inDataLaunch] = 'R'; let outDataWave = Array(timing.totalTicks).fill('.'); outDataWave[0] = '='; outDataWave[indices.outDataLaunch] = 'x'; outDataWave[indices.outDataLaunchMax] = '='; let outDataNode = Array(timing.totalTicks).fill('.'); outDataNode[indices.outDataLaunch] = 'S'; outDataNode[indices.outDataLaunchMax] = 'T'; let inDataWave = Array(timing.totalTicks).fill('.'); inDataWave[0] = '='; inDataWave[indices.inDataLaunch] = 'x'; inDataWave[indices.inDataLaunchMax] = '='; let inDataNode = Array(timing.totalTicks).fill('.'); inDataNode[indices.inDataLaunch] = 'U'; inDataNode[indices.inDataLaunchMax] = 'V'; return { head: { tick: timing.startEdgeIdx }, signal: [ { name: params.RefClk, wave: refClkWave.join(''), node: refClkNode.join('') }, { name: params.OutClk, wave: outClkWave.join(''), node: outClkNode.join('') }, { name: params.OutData, wave: outDataWave.join(''), node: outDataNode.join('') }, { name: params.InData, wave: inDataWave.join(''), node: inDataNode.join('') } ], edge: [ refClkNode[indices.outDataLaunch] + '->' + outDataNode[indices.outDataLaunch], refClkNode[indices.outDataLaunch] + '->' + outDataNode[indices.outDataLaunchMax], outDataNode[indices.outDataLaunchMax] + '->' + outClkNode[indices.outDataLatchSetup], outDataNode[indices.outDataLaunch] + '->' + outClkNode[indices.outDataLatchHold], outClkNode[indices.inDataLaunch] + '->' + inDataNode[indices.inDataLaunch], outClkNode[indices.inDataLaunch] + '->' + inDataNode[indices.inDataLaunchMax], inDataNode[indices.inDataLaunchMax] + '~>' + refClkNode[indices.inDataLatchSetup], inDataNode[indices.inDataLaunch] + '~>' + refClkNode[indices.inDataLatchHold] ] } }38:[] 30:{"id":"68927c95e571e020","slug":"spi-timing-constraints","title":"SPI Timing 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timing.startEdgeIdx,\n outClkRe : timing.outClkRe - timing.startEdgeIdx,\n outClkFe : timing.outClkFe - timing.startEdgeIdx};\n}","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","providerMetadata":"$undefined","attachments":"$undefined","output":"$undefined","database":"$undefined"},{"id":200,"value":"$37","pinned":false,"hidden":false,"mode":"ojs","author":"$undefined","summary":"$undefined","providerMetadata":"$undefined","attachments":"$undefined","output":"$undefined","database":"$undefined"}],"files":"$W38","stdlib":"1"}} 31:"$30:body"