wd({reg:[
{bits: 7, name: 0b1010111, attr: 'vsetvl'},
{bits: 5, name: 'rd', type: 4},
{bits: 3, name: 7},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'rs2', type: 4},
{bits: 6, name: 0b1000000},
{bits: 1, name: 1},
], config: {bits: 32, hspace: width}})