Published
Edited
May 20, 2020
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R({
C: { // name of node
sources: ['osc.out'],
exports: ['uart0.clk', 'uart1.clk', 'pcie.clock1', 'pcie.clock2']
// other parameters
}
})
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R({
C: {
sources: ['osc.out'],
exports: ['uart0.clk', 'uart1.clk', 'pcie.clock1', 'pcie.clock2'],

div: 4, // 4-bit divider inside
}
})
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R({
C: {
sources: ['ro.cout', 'osc.out'], // 2 input mux
exports: ['uart0.clk', 'uart1.clk', 'pcie.clock1', 'pcie.clock2'],

div: 4,
gate: true, // clock gate
}
})
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R({
OSC: {
sources: ['osc.out'],
// not export
div: 4 // pre-divider
},
C: {
sources: ['ro.cout', 'OSC'], // 2 input mux
exports: ['uart0.clk', 'uart1.clk', 'pcie.clock1', 'pcie.clock2'],
div: 6, // common divider
}
})
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R({
pll_feed: {
sources: ['osc.out'],
exports: ['pll.clk_input']
},
central: { // name of node
sources: ['ro.cout', 'osc.out', 'pll.clk_output'], // 3 input mux
div: 4, // 4-bit divider
exports: ['uart0.clk', 'uart1.clk', 'pcie.clock1', 'pcie.clock2'] // 4 clock gating cells
}
})
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R({
ABC: {sources: ['osc.out', 'RO.out', 'pinmux.clk0', 'pinmux.clk1', 'pinmux.clk2']},
AD: {sources: ['osc.out', '???', 'ABC']},
EE: {sources: ['osc.out'], exports: ['pll.clk_input']},
C0: {sources: ['AD'], exports: ['c0.clk', 'c1.clk', 'c2.clk', 'c3.clk']},
C1: {sources: ['AD'], exports: ['c4.clk', 'c5.clk', 'c6.clk', 'c7.clk']}
})
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xbar = grender(g => {
const targets = _.range(3).map(t => g('t' + t)());
_.range(5).map(i => {
const nd = g();
targets.map(t => t(nd));
nd()(g('i' + i));
});
})
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