Iron-based life form descended from T-72
Public
Edited
Jan 21, 2023
2 stars
wd(
{reg:[
{name: 'opcode', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: 0},
{name: 'rs1', bits: 5, attr: 0},
{name: 'imm', bits: 12, attr: 0}
], config: {hspace: width}}
)
wd(
{reg: [
{name: 'OP-IMM', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},
{bits: 17}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP-IMM', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
{bits: 10},
{name: 'imm?', bits: 7, attr: [0, 0, 32]}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'opcode', bits: 7, attr: ['AUIPC', 'LUI']},
{name: 'rd', bits: 5, attr: 0},
{bits: 20}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP', bits: 7, attr: 0b0110011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ')},
{bits: 10},
{name: 'func7', bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}
], config: {hspace: width}}
)
RV32I = (
6 * (1 << 17) +
3 * (1 << 10) +
2 * (1 << 20) +
10 * (1 << 10)
)
wd(
{reg:[
{name: 'OP-IMM-32', bits: 7, attr: 0b0011011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: 'ADDIW'},
{bits: 17}
], config: {hspace: width}}
)
wd(
{reg: [
{name: 'OP-IMM', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
{bits: 10},
{name: 'imm?', bits: 7, attr: [1, 33, 33]}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP-IMM-32', bits: 7, attr: 0b0011011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: ['SLLIW', 'SRLIW', 'SRAIW']},
{bits: 10},
{name: 'imm?', bits: 7, attr: [0, 32, 32]}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP-32', bits: 7, attr: 0b0111011},
{name: 'rd', bits: 5, attr: 0},
{name: 'func3', bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},
{bits: 10},
{name: 'func7', bits: 7, attr: [0, 0, 32, 0, 32]}
], config: {hspace: width}}
)
RV64I = (
(1 << 17) +
3 * (1 << 10) +
2 * (1 << 10) +
5 * (1 << 10)
)
wd(
{reg:[
{name: 'OP-IMM', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: ['ADDI', 'XORI', 'ORI']},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'imm', bits: 12, attr: 0}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP-IMM', bits: 7, attr: 0b0010011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: 'ANDI'},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'imm', bits: 12, attr: -1}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP', bits: 7, attr: 0b0110011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: 'ADD SUB OR XOR SLL SRL SRA'.split(' ')},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'rs2', bits: 5, attr: 0},
{name: 'func7', bits: 7, attr: [0, 0, 0, 0, 0, 32, 32]}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP', bits: 7, attr: 0b0110011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: ['ADD', 'OR', 'XOR']},
{name: 'rs1', bits: 5, attr: 0},
{name: 'rs2', bits: 5, attr: 'A'},
{name: 'func7', bits: 7, attr: 0}
], config: {hspace: width}}
)
wd(
{reg:[
{name: 'OP', bits: 7, attr: 0b0110011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: ['AND', 'OR']},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'rs2', bits: 5, attr: 'A'},
{name: 'func7', bits: 7, attr: 0}
], config: {hspace: width}
})
RV32I_extra = (
3 * 31 +
31 +
7 * 31 +
3 * 31 +
2 * 31
)
wd(
{reg: [
{name: 'OP-IMM-32', bits: 7, attr: 0b0011011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: ['ADDIW', 'SLLIW', 'SRLIW', 'SRAIW']},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'imm', bits: 12, attr: 0}
], config: {hspace: width}
})
wd(
{reg: [
{name: 'OP-32', bits: 7, attr: 0b0011011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: ['ADDW', 'SUBW', 'SLLW', 'SRLW', 'SRAW']},
{name: 'rs1', bits: 5, attr: 'A'},
{name: 'rs2', bits: 5, attr: 0},
{name: 'imm', bits: 7, attr: [0, 0, 0, 32, 32]}
], config: {hspace: width}}
)
wd(
{reg: [
{name: 'OP', bits: 7, attr: 0b0011011},
{name: 'rd', bits: 5, attr: 'A'},
{name: 'func3', bits: 3, attr: 'ADDW'},
{name: 'rs1', bits: 5, attr: 0},
{name: 'rs2', bits: 5, attr: 'A'},
{name: 'func7', bits: 7, attr: 0}
], config: {hspace: width}
}
)
RV64I_extra = (
4 * 31 +
5 * 31 +
31
)
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