Iron-based life form descended from T-72
Public
Edited
Jun 5, 2023
1 star
SekvencoAXI4WaveDrom Release NotesAHBPiecewiseRISC-V-V OPCODESHandshake annotationbitfield testboxWaveDrom schemaTileLink timingonml + tspanLogic Gate TablesRISC-V Spec DiagramsCircular Graph Layoutbit-fieldReqAck -- leading zeros counterDiagrams and system visualisation in chip designWaveDrom arkWaveDrom LambdaHitchhiker's Guide to the WaveDromHitchhiker's Guide to the WaveDrom (Part 2)Motorola S-recordRISC-V "V"QuarkNOP-V
Bit-Field guide
Also listed in…
bitfield
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-IMM'},
{bits: 5, name: 'rd', attr: 'dest'},
{bits: 3, name: 'func3', attr: ['ADDI', 'SLTI', 'SLTIU', 'ANDI', 'ORI', 'XORI'], type: 4},
{bits: 5, name: 'rs1', attr: 'src'},
{bits: 12, name: 'imm[11:0]', attr: 'I-immediate[11:0]', type: 3}
], config: {hspace: width}}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-IMM'},
{bits: 5, name: 'rd', attr: 'dest'},
{bits: 3, name: 'func3', attr: ['SLLI', 'SRLI', 'SRAI'], type: 4},
{bits: 5, name: 'rs1', attr: 'src'},
{bits: 5, name: 'imm[4:0]', attr: 'shamt[4:0]'},
{bits: 7, name: 'imm[11:5]', attr: [0, 0, 32]}
], config: {hspace: width}}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: ['LUI', 'AUIPC']},
{bits: 5, name: 'rd', attr: 'dest'},
{bits: 20, name: 'imm[31:12]', attr: 'U-immediate[31:12]', type: 3}
], config: {hspace: width}}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'OP'},
{bits: 5, name: 'rd', attr: 'dest'},
{bits: 3, name: 'func3', attr: 'ADD SLT SLTU AND OR XOR SLL SRL SUB SRA'.split(' '), type: 4},
{bits: 5, name: 'rs1', attr: 'src1'},
{bits: 5, name: 'rs2', attr: 'src2'},
{bits: 7, name: 'funct7', attr: [0, 0, 0, 0, 0, 0, 0, 0, 32, 32]}
], config: {hspace: width}}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-IMM'},
{bits: 5, name: 'rd', attr: 0},
{bits: 3, name: 'func3', attr: 'ADDI', type: 4},
{bits: 5, name: 'rs1', attr: 0},
{bits: 12, name: 'imm[11:0]', attr: 0, type: 3}
], config: {hspace: width}}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'BRANCH'},
{bits: 5, name: 'imm', attr: 'offset[11|4:1]', type: 7},
{bits: 3, name: 'func3', attr: ['BEQ', 'BNE', 'BLT', 'BLTU', 'BGE', 'BGEU'], type: 4},
{bits: 5, name: 'rs1', attr: 'src1'},
{bits: 5, name: 'rs2', attr: 'src2'},
{bits: 7, name: 'imm', attr: 'offset[12|10:5]', type: 3}
]}
)
wd(
{reg: [
{bits: 7, name: 'opcode', attr: 'BRANCH'},
{bits: 1, name: '[11]', type: 3},
{bits: 1, name: '[1]', type: 3},
{bits: 1, name: '[2]', type: 3},
{bits: 1, name: '[3]', type: 3},
{bits: 1, name: '[4]', type: 3},
{bits: 3, name: 'func3', attr: ['BEQ', 'BNE', 'BLT', 'BLTU', 'BGE', 'BGEU'], type: 4},
{bits: 5, name: 'rs1', attr: 'src1'},
{bits: 5, name: 'rs2', attr: 'src2'},
{bits: 1, name: '[5]', type: 3},
{bits: 1, name: '[6]', type: 3},
{bits: 1, name: '[7]', type: 3},
{bits: 1, name: '[8]', type: 3},
{bits: 1, name: '[9]', type: 3},
{bits: 1, name: '[10]', type: 3},
{bits: 1, name: '[12]', type: 3}
]}
)
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